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uart_tran
- UART串口的传送verilog原程序，已经经过了编译仿真-Verilog UART serial transmission of the original procedure has been compiled after a simulation
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
btm_communication
- 自己项目中用到的verilog UART程序。-Their own projects verilog UART procedure used.
usart_verilog
- Uart verilog 代码 可综合 很好的代码-Uart verilog code
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
lab3
- verilog source code for uart design
uart
- uart using verilog hdl
uart
- UART schematic and code
UART
- 简易UART程序 verilog 描述-Simple UART procedure described in verilog
UART_VHDL_Verilog
- UART的Verilog_源码,适合初学者学习can协议。-UART s Verilog source, suitable for beginners can learn from the agreement.
uart
- This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
sdram32
- DDR SDRAM source verilog source codes
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
uart
- fpga 串行口 接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
UART
- 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
au
- 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog